Investigation into the DDC concept

The concept of Digital Down Conversion (DDC) is not new to me. I had been early adopter of the USRP1, and had it running OpenBTS for non ham related R&D projects. The magic of emulating GSM network is orders of magnitude more complex than sampling the full HF spectrum and then presenting a 192k stream to the PC for a software defined receiver program.

But my friend Bri(G0MJI) recently brought my attention to an interesting board called Red Pitaya.


There is nothing extraordinary about it, it is the usual ADC, connected to FPGA with some emulated logic to implement down conversion, with DDS/NCO etc. This one has ARM core cpu inside as well, so it can run Linux on chip, which is a money saver. What was amazing about is that a user called Pavel have managed to create multiband, parallel WSPR receiver – fully contained on board. You need only antenna, power and Ethernet connection!


It is a computing intensive task so active cooling is a must! And it actually happens that this board is quite amazing at WSRP. After maybe week of using it on air I was curious how good/worse is this DDC concept against traditional setup of HF transceiver and a PC.

Although looking at the WSRP spot database it would seems the board performs exceptionally, there is still doubt how sensitive and protected against overloading is an ADC input open to everything from 0 to 60 Mhz. Yes, the ADC on board seems to be clocked at 125 Mhz.

My test setup was the board itself, submitting to, and old Sony Laptop running Ubuntu 14.04 and latest WSJT-X. So the decoder versions on the Red Pitaya and the laptop are compiled from the same source code – the latest K9AN C decoder. Also same antenna is used to feed the mcHF and the RP board, via mini-circuits signal spliter.


The board during day time actually samples and submit eight ham bands, but my setup did the comparison only on 40m as it was not practical to have 8 laptops and transceivers. Here the six consequential screenshots, where on the left you can see spots submitted from the Red Pitaya and on the right local decodes from the mcHF/WSJT-X combination.

Screenshot from 2016-05-17 17_46_55screen 1(click to open high res)

Screenshot from 2016-05-17 17_48_21

screen 2(click to open high res)

Screenshot from 2016-05-17 17_51_02

screen 3(click to open high res)

Screenshot from 2016-05-17 17_52_27

screen 4(click to open high res)

Screenshot from 2016-05-17 17_54_35

screen 5(click to open high res)

Screenshot from 2016-05-17 17_56_24

screen 6(click to open high res)

So it would seems there is no visible performance problem compared to conventional setup. This could, off course, be attributed to the resilience of the WSPR protocol. But this board demonstrates very extreme case – fully open input of the ADC, directly connected to external antenna. Practical transceiver designs that use the DDC architecture (eg IC-7300, etc..) implement wide range of modules to prevent this – switchable BPFs, pre-amps, digitally controlled attenuators, etc.

So apart from ginormous power consumption, high speed clocks, difficult to route multi-layer PCBs and big chips – the DDC architecture is a clear winner!

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